9. Error Protection and Handling

9.6 CP0 Status Register DE Bit

Asserting the CP0 Status register DE bit suppresses the posting of future Cache Error exceptions. All local CacheErr registers are also prevented from being updated. Unlike the R4400 processor architecture, when the DE bit is asserted, cache hits are not inhibited when an uncorrectable error is detected. Correctable errors are handled normally when the DE bit is set.

NOTE: Be careful when setting this bit, since it may cause erroneous data and/or instructions to be propagated.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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